Semiconductors
Semiconductors
What goes wrong
Failure modes we test for
- Solder-joint cracking and interfacial delamination in IC packages under thermal stress
- Electrical drift in power devices during high-temperature ageing
- Accuracy degradation in MEMS and optical modules under accelerated ageing
- Throughput limits in wafer-level thermal screening
Test scenarios and what the solution gives you
Aimed at the whole semiconductor chain, from front-end wafer fabrication to back-end assembly and test.
Accelerated ageing coupled with thermal stress quickly exposes interfacial delamination, solder fatigue, package cracking and electrical drift, delivering reliability data before a product goes to volume.
Test objects
What we test
- IC, SoC and MCU devices
- Power devices: IGBT, SiC, GaN
- PCB and PCBA assemblies
- MEMS sensors and optical modules
- Packaging materials and lead frames
- Wafer-level test samples
Standards
Applicable standards
| JESD22-A104 | Temperature cycling |
|---|---|
| JESD22-A106 | Thermal shock |
| IEC 60068-2 | Environmental testing |
| MIL-STD-883 | Microcircuits |
Solution highlights
How the configuration helps
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Wafer-level screening
Very fast ramping chambers support wafer-level temperature cycling at roughly ten times the throughput
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Package reliability
Thermal shock exposes delamination, solder cracking and interfacial failure
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Power device ageing
HAST verifies long-term electrical stability of power devices under bias
Discuss your test programme
Send the standard and the specimen, and we will map it onto a chamber configuration with the evidence your reviewer will ask for.